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Embedded Stripline Impedance, Reference Plane Questions

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Advanced Member level 2
Dec 24, 2005
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I am a HW designer. Recently a customer asked us to design an interface board that combines some high speed (250MHZ max) signals that we produce with some very low speed microcontroller circuits that they designed. The want a separate power and ground plane for their stuff and want these planes DC isolated from our nets. While on vacation, my boss instructed the PCB designer to place one of our high speed net layers between our ground and the customer ground plane.

Target impedance is 50 ohms. Trace width is 0.155mm. Spacing to customer ground is 0.100mm. Spacing to our ground is 0.110mm.

My opinion is that the signal layer is approximately equal distance between the planes and will attempt to reference both equally. Since there is no path for the return currents on the customer ground plane, I suspect this will cause signal integrity issues as the signals enter and exit the interface board. High speed signal loads is through a coax cable assembly.

My boss believes in intelligent electrons. He thinks the return current will flow only on our ground layer and avoid the customer's ground layer. He refuses to allow me to decouple the two ground planes at the input and output connectors and told the PCB designer to go ahead.


1. What layers do the return currents flow on in an embedded stripline?
2. Are there any textbooks or web articles that discuss embedded striplines between two planes where one plane is electrically isolated?
3. Are there any freeware software to model this?

Thanks for any pointer or help.

From the stuff I've read on the subject the return currents take the lowest impedance path. In your case that would be your ground plane. There will likey be some impact if their reference plane isn't truly electrically isolated from your ground (e.g. grounds tied someplace else, perhaps through an external power strip). I'd suggest running a simulation on the design to see if there is any effect.

I tried previously to simulate this with LTSpice. I modeled the PCB trace as two 100 ohm transmission lines in parallel. In the simulation, it I floated one side of the transmission line, then I got lots of reflections,etc. Connecting one with a small value inductor also showed lots of signal integrity issues.

Is there a better model in Spice to simulate this? Or a different way to do it?

The rule of thumb that it follows the path of least inductance suggests that the signal is being propagated mainly by a magnetic field. This magnetic field will wrap around the signal conductor as concentric circles with the conductor in the center. Since the planes are roughly equal distance, the same number of magnetic field lines will cut across the upper plane as the lower plane. This in turn suggest that the induced current in the planes is roughly equal. That fact that one plane is attached to the same ground as the signal driving the conductor is not a big contributor. If we had to reference the same ground to magnetically couple a current then power transformers would not work. So I am back to my original thought that this will give the board signal integrity problems.

It will couple to both planes, not the best solution... and will add some noise and signal integrity issues, for the top plane it is similar to having a huge slot in your ground plane. It would have been better to put the signals between your power and ground planes.
If planes are over each other they will capacitivly couple, this is one of the best methods of transferring noise from one section to another... not good for EMC.

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