Elevator controller problem with the counter

[yentran]

I have a class project which is "16 stories elevator controller ". I have a problem with the counter issued. For example, I set switch to get to a desired floor is 6, and the counter count-up from 1 2 3 4 5 6 and count down to 5. Here is my following code.
module top_module(
input [3:0] iSw,
input iGo,
input clk,
input iRst,
output [3:0] cFloor
);

wire [3:0] odFloor;
wire up_down;
wire oeq;
wire orun;
wire ogo;

comp4 inst1 ( .iP(odFloor), .iQ(cFloor), .oPgtQ(up_down), .oPeqQ(oeq));
floor_cnt inst2 ( .clk(clk), .rst(iRst), .en(orun), .act(up_down), .cFloor(cFloor));
fsm inst3 (.clk(clk), .go(ogo), .eq(oeq), .rst(iRst), .done(), .run(orun), .open());
L2P inst4 ( .clk(clk), .rst(iRst), .L(iGo), .P(ogo));
vreg inst5 (.iSw(iSw), .rst(iRst), .clk(clk), .mode(ogo), .dFloor(odFloor));

endmodule

module comp4(
input [3:0] iP,
input [3:0] iQ,
output oPgtQ,
output oPeqQ
);

// Add internal wires
wire [3:1] PgtQ, PeqQ;

// Instantiate to comp1 to create 4-bit iterative comparator
comp1 comp1_3_i (.iP(iP[3]), .iQ(iQ[3]), .iPgtQ(1'b0), .iPeqQ(1'b1), .oPgtQ(PgtQ[3]), .oPeqQ(PeqQ[3]));
comp1 comp1_2_i (.iP(iP[2]), .iQ(iQ[2]),.iPgtQ(PgtQ[3]), .iPeqQ(PeqQ[3]), .oPgtQ(PgtQ[2]), .oPeqQ(PeqQ[2]));
comp1 comp1_1_i (.iP(iP[1]), .iQ(iQ[1]),.iPgtQ(PgtQ[2]), .iPeqQ(PeqQ[2]), .oPgtQ(PgtQ[1]), .oPeqQ(PeqQ[1]));
comp1 comp1_0_i (.iP(iP[0]), .iQ(iQ[0]),.iPgtQ(PgtQ[1]), .iPeqQ(PeqQ[1]), .oPgtQ(oPgtQ), .oPeqQ(oPeqQ));

endmodule

module comp1(
input iP,
input iQ,
input iPgtQ,
input iPeqQ,
output oPgtQ,
output oPeqQ
);

assign oPgtQ = iPgtQ | iPeqQ & (iP & ~ iQ) ;
assign oPeqQ = ~iPgtQ & iPeqQ & (~iP ^ iQ);

endmodule

/* This is a floor counter machine. When the signal 'act' in high,the counter will count up and vice versa */

module floor_cnt(
input clk,
input rst,
input en,
input act,
output reg [3:0] cFloor
);

always@(posedge clk, posedge rst)
if (rst)
cFloor <= 0;

else if (en)
if (act)
begin
cFloor <= cFloor +1;
end
else
begin
cFloor <= cFloor -1;
end


endmodule

/*This is a state machine for the elevator */
module fsm(
input clk,
input go,
input eq,
input rst,
input done,
output run,
output open
);

parameter S_W4go = 2'b00; // state at the door close and wait for input
parameter S_run = 2'b01; // state at the door close and the elevator runs after input is asserted
parameter S_open = 2'b10; // state at the door is open when input is at the right floor

reg [2:0] state, next_state;
//--------------------------------------------------------------//
// Sequential logic
//--------------------------------------------------------------//
always @(posedge clk, posedge rst)
if (rst)
state <= S_W4go;
else
state <= next_state;
//--------------------------------------------------------------//
// Next state logic
//-------------------------------------------------------------//
always @(*)
if (rst) next_state <= S_W4go;
else case (state)
S_W4go: if (go) next_state <= S_run;
else next_state <= S_W4go;
S_run: if (eq) next_state <= S_open;
else next_state <= S_run;
S_open: if (done) next_state <= S_W4go;
else next_state <= S_open;
default: next_state <= S_W4go;

endcase
//----------------------------//
// Output logic
//----------------------------//
assign run = (state==S_run);
assign open = (state==S_open);


endmodule

/* This is level to pulse module which is the input high for 3 consecutive clock will
generate an output high*/
module L2P(
input clk,
input rst,
input L,
output P);

reg [2:0] state, next_state;
// parameter [2:0] S0=000, S1=001, S2=010, S3=011, S4=100;
parameter [2:0] S0=0, S1=1, S2=2, S3=3, S4=4;
//-------------------------------------------//
// Define the next state combinational circuit
always@(L,state)
case(state)
S0: if(L)
next_state = S1;
else
next_state = S0;

S1: if(L)
next_state = S2;
else
next_state = S0;

S2: if(L)
next_state = S3;
else
next_state = S0;

S3: if(L)
next_state = S4;
else
next_state = S0;

S4: if(L)
next_state = S4;
else
next_state = S0;

default: next_state= 3'bxxx;
endcase

//-------------------------------------------//
// Define the sequential block
always@ (posedge rst, posedge clk)
if(rst)
state <= S0;
else
state <= next_state;

//-----------------------------------------//
// Define output
assign P =(state==S3);

endmodule

/* this is a 4-bit register paralle loading. If mode is high,the data is loaded by iSw */


module vreg(
input [3:0] iSw,
input rst,
input clk,
input mode,
output reg [3:0] dFloor
);

always @(posedge clk, posedge rst)
if (rst)
dFloor <= 0;
else
if (mode)
begin
dFloor <= iSw;
end

endmodule
/* this is a test fixture */
module top_module_tf;

// Inputs
reg [3:0] iSw;
reg iGo;
reg clk;
reg iRst;

// Outputs
wire [3:0] cFloor;

// Instantiate the Unit Under Test (UUT)
top_module uut (
.iSw(iSw),
.iGo(iGo),
.clk(clk),
.iRst(iRst),
.cFloor(cFloor)
);
always
#10 clk = ~clk;
initial begin
// Initialize Inputs
iSw = 0; iGo = 0; clk = 0; iRst = 1;
#10 iSw =4'd6; iGo=1; iRst =0; clk =1;
#90 iGo =0;


// Wait 100 ns for global reset to finish
#200 $finish;



end

endmodule


// Thanks in advance everybody !!!

 

[mrflibble]

Best use meaningful names for instances. You made me actually look at the source code to find out what inst1,2,3,4,5 etc were.

inst3 insn't very informative, while fsm, fsminst, myfsm, etc might give you a hint that this is an instance of the fsm module.

That, and the done input to your fsm instance unconnected. And quick glance at your code tells me that the fsm action does actually depend on it's value. So that's probably a good place to start looking.