modsRule
Newbie level 3
I am looking for a nice way to write a short std_logic_vector to a specific location in a larger std_logic_vector using VHDL.
For example:
But there must be a neater way, especially if the vectors were larger than in this example.
For example:
Code:
--If I define a port CTRL such that
CTRL : out STD_LOGIC_VECTOR (15 downto 0);
--And a signal posmul0
signal posmul0 : STD_LOGIC_VECTOR (2 downto 0);
--And want to then write posmul0 into CTRL in locations [3:1], whilst setting CTRL[0] to '1'
--I could do it like this:
CTRL(0) <= '1';
CTRL(1) <= posmul0(0);
CTRL(2) <= posmul0(1);
CTRL(3) <= posmul0(2);But there must be a neater way, especially if the vectors were larger than in this example.