Electro-migration and max fT in RF-CMOS pcell

[skal81]

I am designing RF CMOS circuit and have a question regarding electro-migration in the transistor.

To have accurate simulation, I am using the foundry provided pcell.
Referring to the sample data in the manual, I select the bias current to have maximum fT.
For example, I need 5mA to achieve 100GHz fT is one technology.
However, when I checked the pcell layout, I noticed that the metal 1 at the drain is of minimum width.
If I calculate the maximum current to respect EM rules, it was much more smaller than the current to achieve max fT. Even using many fingers, I cannot achieve max fT.
For example, the maximum current is 1.5mA, which would correspond to only an fT of 40GHz.

In the model data and other documents, high bias samples were available, so I asked the foundry about the EM issue. The only answer I could have was that samples are just samples, and that I need to respect EM rules.
This does means that I cannot use the transistor at it's max fT.

By the way, I tried to check other processes, and the results was the same.

Does anyone ever notice such a problem? Does anyone have any good solution?

Thank you in advance.

 

[erikl]

Can you stack & connect higher metal levels in parallel? Some more parasitics, of course.

 

[skal81]

Thank you for your idea.
It is indeed one solution I was thinking of. The main problem is that by changing the metals I could not use the foundry's models anymore. I am thinking to try to do electromagnetic simulation of the modified cell, but I am not sure of the results yet.
Do you have any experience of changing the pcell layout?

 

[erikl]

Do you have any experience of changing the pcell layout?

A bit. You have to smash the pCell, then you should be able to handle it like your hand-made layouts. ERC rules will check the EM compatibility, whereas the extract tool will extract the parasitics for post-layout simulation (and use the extracted_view for LVS).

 

[dick_freebird]

You should expect that to get the last bit of bandwidth,
modeled accurately, you will have to go beyond the PCell
that somebody else made for you. It's the norm in RF switch
design, to spend as much time in electromagnetic analysis
as plain circuit design. Especially once you start stacking
FETs and hoping that you'll retain the reliability that your
simple starting assumptions (such as equal voltage division)
made you think possible.

You should look at your elements of Cgd/Cgs and see how
much of that is really metal-poly fringing. This may respond
well to added spacing above what the packed PCell gives,
and you can make room for more S/D width perhaps (though
in bulk CMOS, growing the S/D junction area is not going to
help distortion any). In a silicided S/D process (which most
are now) you might even consider sparse contacts and
chimney via-stacks up to higher metal to relieve the Cgd/Cgs.
Up to the point where that becomes a meaningful insertion
loss contributor.

Last, do not let anyone conflate DC electromigration rules
with RF electromigration limited AC current carrying capability.
They are very different, in the numbers. Demand data and
analysis that shows setup and work, so you know you're
not being sandbagged or tasked by plastered-over errors.

 

[skal81]

To erikl >
Thank you for the information. I will give it a try.

To dick_freebird >
Thank you for your advice.
About the electromagnetic analysis results, I am not familiar yet this detailed analysis. I mean that I usually use it for inter-devices connections. Most of the time, vias are merged and the grid is wider for big large metals. I think that if I want to do characterization of the transistor, I must keep non merged vias and fine grid. Would the tool be able to solve that (in the past I had bad experience of days of calculation ending this memory error...)
What tool do you usually use? Did you saw good correlation in between simulation and measurements?

If you have any opinion, please let me know.

Thank you in advance.
Regards