Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

efficient parallel real time upsampling

Status
Not open for further replies.

lgeorge123

Full Member level 2
Joined
Jun 13, 2004
Messages
130
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Location
Hong Kong
Activity points
1,403
Under this article using xilinx FPGA , a process is only to implement a upsample factor of 4 ,a 16 FIR filter coefficients are used, so what if a upsamle factor is 10 , is it need to use 100 fir filter coefficients ?
 

Attachments

  • efficient-parallel-real-time-upsampling-with-xilinx-fpgas.pdf
    977.6 KB · Views: 47

Hi,

No. FIR filter coefficients count is independent of sampling rate. It depends on filter characteristic.
But if you change sampling rate you need to adjust filter coefficients (value) to get the same filter characteristic.

Klaus
 
So please give me some advice , if the up sampling factor is 10 , what is the number of fir filtering coefficients?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top