efficiency of ac/dc using active comparator

[bll_hb]

Hello guys,

I am going to design ac/dc circuit low freq and min input voltage.

the efficiency of schematic of the circuit using cadence is about 81%

but when i run process corner the efficiency of post layout become low around 40% at high temp 27c, and at low temp -40c the efficiency is 71%


my question why at low temp efficiency is high then at high temp?

 

[erikl]

... why at low temp efficiency is high then at high temp?

Less leakage currents of necessary and parasitic devices.