gilbertomaldito
Full Member level 3
Hi
I wanna ask if how the parasitic inductance of a bonding wire in the Vdd and Gnd pins affect the performance of a differential circuit structure especially on the differential output. I actually simulated a differential transmitter (LVDS) and tried to put parasitic L on vdd and gnd rails. I observed that the jitter at the output worsens. Im just confused, since it is a differential structure, how come it is affected ? Also Iwant to ask, how can I check the PSRR of my LVDS transmitter?
Thank you
andrew
I wanna ask if how the parasitic inductance of a bonding wire in the Vdd and Gnd pins affect the performance of a differential circuit structure especially on the differential output. I actually simulated a differential transmitter (LVDS) and tried to put parasitic L on vdd and gnd rails. I observed that the jitter at the output worsens. Im just confused, since it is a differential structure, how come it is affected ? Also Iwant to ask, how can I check the PSRR of my LVDS transmitter?
Thank you
andrew