Effects of connecting GNDA and GNDD at the chip and at the board level

[surianova]

hi all!

i have 2 GND. One is analog gnd, GNDA and the other is digital GND called GNDD.

We know that these 2 GND at the end have to connect at the same common point.

These 2 GND (GNDA and GNDD) shd connect at the chip/die level or at the board level?

Any difference when you connect at the chip or board level?

For your information, my circuit is very sensitive to noise.

 

[IanP]

Re: GND issue

If digital section on your pcb does not have ground plane then chip level is probably better option ..
If it does then pcb level should solve the issue ..

Also, see:
**broken link removed**

Rgds,
IanP

 

[saro_k_82]

Re: GND issue

See whether you can provide a low impedance ground inside the chip. How low this low impedance be depends on the digital side current. The best thing would be to have a ground plane on the PCB with two grounds and connecting the GNDA and GNDD right at the bottom of ADC.
In case you don't have a GND plane, it's simple math to find out which is the better option by computing the resistances and the current flow(Ignoring inductance.., which you can't if your frequency or currents are high., but in that case you should be going for a GND plane).

 

[surianova]

Re: GND issue

See whether you can provide a low impedance ground inside the chip. How low this low impedance be depends on the digital side current. The best thing would be to have a ground plane on the PCB with two grounds and connecting the GNDA and GNDD right at the bottom of ADC.
In case you don't have a GND plane, it's simple math to find out which is the better option by computing the resistances and the current flow(Ignoring inductance.., which you can't if your frequency or currents are high., but in that case you should be going for a GND plane).

Below is the statament i found out when we connect GNDA and GNDD at board rather chip level but i am not realy understans :

These grounds need to connect somewhere for the circuit to have a valid current return path. If they are connected on board, rather than the die, there may be substantial inductive and resistive parasitics,

 

[saro_k_82]

Re: GND issue

That statement is for a PCB that does not employ a GND plane.
Inductance is high because you may have a big supply current loop that invites high frequency noise. Even there you could do your best by placing the ADC very close to the GND entry (or on-board regulator) and use thick track and route VDD and GND very close to each other.
You can forget about the inductance and resistance if you have a good continuous ground plane.

 

[surianova]

Re: GND issue

That statement is for a PCB that does not employ a GND plane.
Inductance is high because you may have a big supply current loop that invites high frequency noise. Even there you could do your best by placing the ADC very close to the GND entry (or on-board regulator) and use thick track and route VDD and GND very close to each other.
You can forget about the inductance and resistance if you have a good continuous ground plane.

ok, actually what is the meaning by valid current return path for GND?

 

[saro_k_82]

Re: GND issue

Current flows in a loop. So only when you close the loop you have a valid current path. This is the reason why you need to connect both the grounds. I don't know how to simplify it. Let me answer as you ask furthur ...

 

[surianova]

Re: GND issue

Current flows in a loop. So only when you close the loop you have a valid current path. This is the reason why you need to connect both the grounds. I don't know how to simplify it. Let me answer as you ask furthur ...

if i connect the GNDA and GNDD at the board level, the current still in the loop, rite?

 

[saro_k_82]

Re: GND issue

YES. That is why it is said 'some where in the path'

 

[surianova]

Re: GND issue

YES. That is why it is said 'some where in the path'

Under what condition we can said current not return to the GND ?Any example?

thanks.

 

[haff99]

Re: GND issue

You are most likely going to have to have to some how tie the grounds together on the chip. The main issue is going to be ESD testing. They are not going to tie the grounds together for ESD testing at the chip level. If your ESD device goes to digital ground for instance, and they zap a pin with respect to analog ground with DGND floating, your ESD device is useless since you have no path to AGND. The path to AGND is going to be through some tub breakdown or something which is probably going to damage your part. So if you do not have the grounds somehow tied on the chip level, the usual way is back to back diodes, you are probably going to fail ESD testing.

So you should have at minimum a back to back diode connection between your grounds. That should be the only interaction between the grounds on the chip level.

 

[surianova]

Re: GND issue

You are most likely going to have to have to some how tie the grounds together on the chip. The main issue is going to be ESD testing. They are not going to tie the grounds together for ESD testing at the chip level. If your ESD device goes to digital ground for instance, and they zap a pin with respect to analog ground with DGND floating, your ESD device is useless since you have no path to AGND. The path to AGND is going to be through some tub breakdown or something which is probably going to damage your part. So if you do not have the grounds somehow tied on the chip level, the usual way is back to back diodes, you are probably going to fail ESD testing.

So you should have at minimum a back to back diode connection between your grounds. That should be the only interaction between the grounds on the chip level.

yes, i agree with that. The Gnd for ESD shd be separate from GNDA and GNDD, because when ESD strike, the current shd flow out of the chip to external GND. If not, it will damage the chip.

I just have the idea abt how non-return current to source's example, but i am not sure is it correct and pls verify

Let say we have 2 GND in our chip.. GNDA and GNDB. And both of them will go to their own bondpad and will only tied together at external GND at Board.

Let say the block that use GNDB, have the switching activity,charging and discharging capacitor and they is overlap between GNDA and GNDB in the layout
( i mean maybe GNDA is in M1 and GNDB is in M2 and separate by oxide). When the cap that using GNDB discharge, it will chose the path has lesser impedance, if GNDA has less impedance, the current from cap will discharge through stray cap to GNDA at high frequency. That mean the current of GNDB wlll couple to GNDA through Stray cap at high frequency.

So, this will create a big loop of current or ground loop. With this big loop, it will cause big electromagnetic field, inductance become higher and this will cause cross talk as well.

Is it the meaning when current non-return to source? Suppose the current go to GNDB but instead go the GNDA.

Any opinion abt this? appreciate ur feedback and opinion. Thanks

 

[ESDSolutions]

Re: GND issue

Hi

My experience is

1.) IC designers for mixed analog-digital applications will tie the different ground pads together inside the package.
This can be a special die cavity or double bond wires. Both may be expensive techniques that you need to check with the assembly house!

This means that AGND, DGND and ESD- or IO-GND are not connected through metal on the chip but are connected together with low resistance bondwire or package ground plane within the package. This should be good enough as most ESD qualification testing is performed at package level

2.) ESD protection between different grounds is still needed
Just think about the assembly process or the die sorting... all involve either humans or machines and can induce ESD stress on the die before it is packaged. This means that ESD protection is required to ensure high enough yield. The approach mentioned before can be used namely anti-parallel diodes. Some even have dual diodes in both directions if the noise is really an issue! Do watch out for parasitic diodes! Just make a cross section, you'll see it!

3.) Protect the sensitive element with ESD clamps that are correctly referenced
If you protect the analog IO with an ESD clamp to ESD_GND then you basically add additional voltage drop for the ESD current. A direct reference between analog_IO and AGND is better for ESD.
You can look at it as follows: The (ESD) current will 'search' for the path with the least voltage drop. If you are working in a 130nm technology with a thin oxide transistor at the analog_IO then this gate oxide will be damaged once the gate-drain or gate-source voltage is above 6V. This means that the ESD protection elements connected in parallel should always have a lower voltage. Please check the TLP curves for the different ESD devices. Your foundry should be able to provide this.

Many ESD problems I have seen are in the analog_IO section due to wrongly referenced protection, underestimation of ESD voltage drop, or the use of very sensitive core transistors connected directly to path for which most foundries do not provide ESD rules.

 

[haff99]

Re: GND issue

In regards to the ESD ground.

Lets say you only have two grounds DGND(digital ground) and AGND(analog ground). Your ESD devices are going to be tied to one of the ground lets say DGND for this example. Now if the Grounds have seperate bond pads and are bonded to different pins, you are going to have to have some sort connection between the grounds on chip. In my example an ESD strike on a pin with respect to DGND is taken care of by the ESD device tied to DGND. What happens if you take that same pin and zap it with respect to AGND? Your ESD device isn't going to protect anything since you have no path from the ESD device to AGND.

What is typically done is you place back to back diodes between AGND and DGND. Now if your zap your pin with respect to AGND, you current flows through the ESD device to DGND through the diode and then to AGND.

You will not got current flowing from DGND to AGND and vice versa during normal operation due to the diodes unless you have large deltas between the grounds on the order of diode drop. If your grounding is done carefully that probably won't happen.

So unless you have some other ESD spec for you chip, other the JEDEC, you are going to have to have to tie your grounds together on chip somehow. When your chip is ESD tested at the chip level by your company, they will zap each pin with respect to each individual ground. That is the JDEC specification. If your compnay will allow ESD testing by tying all the GNDS together, then you have no issue and can keep them totally seperate. However, almost every single IC customer wants IC tested to the JDEC spec. The back to back diodes are the easiest way to connect grounds together on chip while keeping the grounds isolated from each other.

If you had 3 seperate ground bonds going to 3 seperate pins(lets call them DGND, AGND, and PGND) you would have back to back diodes between DGND and AGND and DGND and PGND. Now any zap to a pin with respect to any ground has a path through the ESD device and through the diodes. Again the diodes still allow your grounds to be isolated unless like I said before you have some extremely large differential between the ground where you can somehow forward bias the diodes.

So you really need to find out how your IC is going to be ESD tested before you make your decision.