quaternion
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I am designing on chip LDO.
Is it fair enough in circuit simulation to model the bond wire by a sires inductor then followed by the pad capacitance, knowing that I have only pads models in my PDK(0.13um) ?
Also which pad is used for my case(input voltage could reach 3V )? And what value is suitable for bond wire ?
Is it fair enough in circuit simulation to model the bond wire by a sires inductor then followed by the pad capacitance, knowing that I have only pads models in my PDK(0.13um) ?
Also which pad is used for my case(input voltage could reach 3V )? And what value is suitable for bond wire ?