For CMOS gates, average drive current is C*V*F, where C is the input capacitance, V is supply voltage, and F is clock frequency. It is same for any duty cycle and the current pulses occur during transitions.
This yields total power as CFV^2, neglecting leakage. Leakage becomes a significant issue for deep submicron processes. It starts to become a real issue at 90 nm and smaller geometry. Many submicro IC's have multiple gate oxide thicknesses to control gate threshold. Lower threshold yield faster devices but higher leakage. Higher threshold yields lower leakage but slower devices. The thicker oxide is also necessary for higher voltage I/O's.
For a complex IC the clock tree can be a signficant adder to overall chip power consumption. Branch clock gating is employed to shut down clock to inactive functional blocks in the IC to save power.