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effect of duty cycle on clock power loss

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Mar 1, 2011
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i wanted to know if the duty cycle of the clock signal directly affects the power dissipation??
the duty cycle would define the average voltage over one clock period, so the power loss occurring due to clock power dissipation would depend on the same, wouldn't it??

Any help would be greatly appreciated.


With dependence of situation may be or not. What is scheme of your's application?

For pure logic circuit, its influence should be small if the duty cycle is not close to 0 or 100%.
Let consider CMOS process. If you feed 50% duty cycle clock to inverter what is average current through inverter gets from power supply? Then change the duty cycle to 90% and to 10% you will see the difference is miniskule.
That's because in CMOS it does not depend on voltage level but on the transitions. If you have 0% or 100% dutycycle the same inverter will have Idd=0.
But when you change the switching frequency the IDD will change too. Yes when you VDD will move from 1V to 5V the idd will change also.
Reason is that power consumption of the CMOS inverter is mostly cross currents between VDD and GND (I neglect charging of the gate etc)
that's true.. but what about simple power dissipation of the clock signal due to the transmission wire resistance/impedance?? as heat or other factors?? is that really negligible?? and wouldnt that depend on the average clock voltage over one period?? i'm neglecting the cmos inverter in my thoughts here and just focussing on the propagating clock signal through a wire with finite physical resistance..

Analysis aforementioned assumes no leakage in device that is true for old process.
However, for deep sub-micro process, leakage is becoming bigger and bigger.
If this leakage is considered, duty cycle might affect power consumption.
And wire resistance will also contribute more power consumption.
And wire resistance will also contribute more power consumption.
If length of wire is great. The active resistance is very small, reactive resistance is not power consumption.
The load effects or leakage are not negligible - I just simplified. But at the same time - leakage is significant if you go under 65nm (I doubt people here do anything like that)
Capacitive load - what it does? slows the edges because output fets have to charge the load. So even if I greatly simplified it still holds.
I think this is a good paper:
thanks Teddy.. have u got any more links to good papers on power consumption in CMOS IC's and methods to minimize the same?

This depends on whether your design is level triggered or edge triggered

For CMOS gates, average drive current is C*V*F, where C is the input capacitance, V is supply voltage, and F is clock frequency. It is same for any duty cycle and the current pulses occur during transitions.

This yields total power as CFV^2, neglecting leakage. Leakage becomes a significant issue for deep submicron processes. It starts to become a real issue at 90 nm and smaller geometry. Many submicro IC's have multiple gate oxide thicknesses to control gate threshold. Lower threshold yield faster devices but higher leakage. Higher threshold yields lower leakage but slower devices. The thicker oxide is also necessary for higher voltage I/O's.

For a complex IC the clock tree can be a signficant adder to overall chip power consumption. Branch clock gating is employed to shut down clock to inactive functional blocks in the IC to save power.
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