effect of ADC clock frequency on its linearity

[ansonyeap]

Hello.

Recently I testing an ADC IC. I vary the frequency of the ADC clock frequency and measure the DNL performance. what I notice is that the ADC clock frequency does have significant effect on the DNL performance. I try to find out the explanation behind this but I still cannot solve it.....

Can any one help me with this or maybe suggest where can i get the information related to this. thank you in advance

 

[erikl]

There's always a max. clock frequency, with which the input signal can be sampled and processed. Above this frequency, the converter cannot sample and process the input signal with the necessary accuracy to guarantee the desired resolution. Quite a lot of ADC-internal circuits are responsible for, i.e. determine this max. clock frequency.

Perhaps the PDF below will make this clearer?