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Edge Detect and D Flip Flop from 2:1 Mux

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Newbie level 3
Oct 21, 2007
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Hello all, was hoping someone could help me out with this. I'm trying to figure out how to design a D flip flop using nothing but 2:1 mux(s). Nothing else allowed.

I can see how a latch can be designed using a 2:1 mux where the output responds instantly to the input based on the select line. however, to do this for a flop, one would think you would need some kind of rising edge detect circuitry? Can anyone elaborate? Thanks!

If two latches are connected in master slave combination along with a transmisson gate and the clock signals provided correctly for edge sensitivity(+ve or -ve) then a flop can be constructed.
For the connections refer to ASIC by sebastian smith...
Hope this will clarify your doubt...

Hi all,
Can you post a simple shematic ?
And if possible the exact title of the book.

That looks like it works kanagavel, thanks!

Hi all,
for positive edge triggered dff,
can it be a 2:1 mux, with selectline as clock, input 1= din and input0 = mux output.
Please tell me in case of any corrections.
Thanks in advance.

manasiw2 u cant do that, if u tie the clock to the select pin using a single MUX then if become latch no DFF cause the output will change as long as the input is changing if the clk is still high.
It become level trigger not edge trigger.

I think kanagavel_docs have provide a good solution for this question.

ohh! yes right it is level sensitive latch.

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