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ease to design a common fifo (syn/asyn), not high speed

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CRiSP

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it is ease to design a common fifo(syn/asyn).but,it is difficult to design a high speed fifo.

please share your opinion.
 

cyteng

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How fast do you consider it as "high speed" ?
 

CRiSP

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>300Mhz

for example:it is over 300Mhz.
 

rewkie

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I want to kown how to do?
 

juripero

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Depending on the process you are using, it is relatively simple if you are talking about .15 or .13 CMOS process.
 

gab

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Or you can use a highly pipelined code.
More clock cycles but working over 300 MHz

gab
 

wintel

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i want to know abt the detail architecture of fifo & different types of fifo with design.

Thanx
wintel
 

juripero

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search at TI's site on FIFO design, they have an excellent application note on FIFO architecture and design issues
 

ttspice

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I don't think speed is the issue of FIFO if it is synchronous,
most problem we find is the asynchronous FIFO...

this may help, Mr.Cummings SNUG paper about asyn-FIFO design



attachment deleted. You can find it here: http://www.sunburst-design.com/papers/
(posted 200 times on elektroda)
 

wintel

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give me the detail architecture of synchronous fifo with design
 

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