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haha, e is a verification language belong to candence, in fact ,it found by verisity.
and i known also many people used the systemverilog as verification language.so i wonder the difference between e and sv, and which one will be more pop in future?
haha, e is a verification language belong to candence, in fact ,it found by verisity.
and i known also many people used the systemverilog as verification language.so i wonder the difference between e and sv, and which one will be more pop in future?
e is a verification language used in Specman Elite to allow high-level verification of RTL designs and to analyse functional coverage. It is the property of Cadence, and is in the process of being standardised as IEEE 1647.
It attempts to provide a high level of reuse from the use of 'eVC's or 'e Verification Components'.
Recently, SystemVerilog gains a lot of momentum in verification world. I would like to encourage everyone to learn it since a lot of gurus are backing it and I will see it will replace verilog, VHDL, and E in the next few years.
yes，systemverilog is more popular than e now, but
I think e will have a piece of place in furture because e is a professional verification language, and it will be use by more verification engineer if e become open-code and use free.
The tool is specman, it can work with NC,if you are interesting it,you can connect the local supporter of candence, and this tool is not free, the license cost isn't cheap!
So anyone here used E in an NC tool ? How does it work ? So we can compile & simulate design code (write in Verilog) & testbench code (write in E) in the same tool at the same time ?
specman elite is the tool from veristy which is acquired by cadence.
so it's a cadence tool.
e is the language used.
instead od writing a verilog/vhdl Testbench one writes a e bsed verification environment as it is simpler compared to HDl and the coverage obtained is far more better than HDL based..
Srinivas
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