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Dynamically change of specparam in verilog ?

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tsuresh

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Hi,
My requirement : access time has to change depends on the frequency

Current implementation in short :
==========================
specparam : taccess : 3:4:5

always @(posedge CL)
Q<=D;
==========================
So whenever there is a Clock, I get the valid data in "Q" after "taccess" time.
But this time is fixed as you see from the specparam.
From Design point of view,
there should be two acess time depending on the choosen frequency.
Lets say I have taccess_freq1 and taccess_freq2.
How to model this ?
Can we change specparam dynamically ?
Or some other way is there ?
 

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