Dynamic Reconfigurable Synthesizer IC with High Resolution in Market

[msdarvishi]

Dear everybody,

I am wonder to know whether some Frequency Synthesizer IC are available in market to be able to dynamically reconfigure (change) their operating frequency)? For instance, Suppose that I have a digital design operating at 600MHz frequency that has 1.67 nsec clock frequency. I wan to increase the clock period with around 0.5 nsec to reduce the frequency of synthesizer dynamically. Is there any ASIC frequency synthesizer available in market with this capability?

Thank you,

 

[Dan Mills]

Yea, pleanty, anything from PLLs to full on DDS cores, but hint, you probably want to make the steps powers of two if you can (Or at least integer ratios) in which case a simple syncronous divider and mux may get you what you want.

Simple is usually better then complex in this sort of thing, and 600MHz down to 200MHz is a divide by 3, which is messy but doable, easier targets are 150MHz and 300MHz which sinmply require a couple of D types in the clock path. .

Regards, Dan.

 

[msdarvishi]

Yea, pleanty, anything from PLLs to full on DDS cores, but hint, you probably want to make the steps powers of two if you can (Or at least integer ratios) in which case a simple syncronous divider and mux may get you what you want.

Simple is usually better then complex in this sort of thing, and 600MHz down to 200MHz is a divide by 3, which is messy but doable, easier targets are 150MHz and 300MHz which sinmply require a couple of D types in the clock path. .

Regards, Dan.

@Dan,

Thank you for your reply. I did a lot of searches and I did not find any suitable frequency synthesizer with my desired capability !! Do you know any special product to introduce me?

 

[Dan Mills]

What is your application exactly?
Usually you do not run a 600MHz clock around a board, but instead run something much slower (A few tens of MHz maybe) and PLL it up on the processor or FPGA chip.

Most of the stuff running at 600MHz will have an on chip PLL with a programmable output divider that you can use to slow things down if you need to.

If you really need reconfigurable wide range oscillators (You probablydo not in fact) then what is wrong with the SI570?

There are plenty of others out there, but this is about as easy as it gets.

Regards, Dan.

 

[msdarvishi]

What is your application exactly?
Usually you do not run a 600MHz clock around a board, but instead run something much slower (A few tens of MHz maybe) and PLL it up on the processor or FPGA chip.

Most of the stuff running at 600MHz will have an on chip PLL with a programmable output divider that you can use to slow things down if you need to.

If you really need reconfigurable wide range oscillators (You probablydo not in fact) then what is wrong with the SI570?

There are plenty of others out there, but this is about as easy as it gets.

Regards, Dan.

Thank you Dan for your nice and step-by-step explanation. Actually, I have a logic circuit implemented into Virtex FPGA that I would like to decrease the clock frequency by increasing the clock period for example 0.5 nsec as I explained in my first post. The on-chip PLL associated with Vietex FPGA is limited only to Integer dividers and for the fractionals the value that is added to the peiod (by division) is much larger than 0.5 nsec !! Based on your recent suggestion, can SI570 solve my problem?

Thank you,

 

[Dan Mills]

So you have a pll outputting 600MHz (1.67ns period)?
And you want to go to a period of ~2.2ns, (about 450MHz)?

I would be very surprised if your on chip pll has any trouble at all doing this, don't forget you can fiddle with BOTH feedback and reference dividers to give you a wide range of step sizes (And the PLL core often has a post divider as well).

What is you PLL input clock frequency, and what is the VCO range for your PLL?

The very last thing I would be looking at is messing around with external PLLs, there will be a way to do this on chip, certainally the Altera pll blocks would most likely have no problem doing it (I have no experience with Xylinx parts).

Regards, Dan.

 

[msdarvishi]

So you have a pll outputting 600MHz (1.67ns period)?
And you want to go to a period of ~2.2ns, (about 450MHz)?

I would be very surprised if your on chip pll has any trouble at all doing this, don't forget you can fiddle with BOTH feedback and reference dividers to give you a wide range of step sizes (And the PLL core often has a post divider as well).

What is you PLL input clock frequency, and what is the VCO range for your PLL?

The very last thing I would be looking at is messing around with external PLLs, there will be a way to do this on chip, certainally the Altera pll blocks would most likely have no problem doing it (I have no experience with Xylinx parts).

Regards, Dan.

Dan,

Yes, the PLL is outputting 600MHz. But the problem is than I want to force the PLL/DCM to dynamically reduce the frequency by increasing clock period by 0.5 nsec while the system is running? Is it possible in Virtex-5/Virtex-6 and onward?
I also read the Virtex-6 clock resources user guide carefully and I found that in Virtex-6 only the integer division is supported ! I also read an Application note abbout Dynamic Reconfiguration Port for MMCM and PLL but I am confused how to decrease the frequency? Do you have a good reference to help me or can you explain me that, please?

Thank you,

 

[msdarvishi]

Hi Dan,

Indeed, I need the frequency change in a small range. The problem stated with Si570 is that for a small change in frequency (Tclknew = Tclkold +Delta t , Delta t = 0.5nsec) the frequency range is 3500ppm which means the frequency can change with the factor of 0.35%. but when I add 0.5nsec to the period of a 600MHz clock signal (i.e. 1.66nsec), the frequency will change with the factor of 30%. It means that Si570 is so far than this value. Is there any alternative for that?

Thanks,

 

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I also read the Virtex-6 clock resources user guide carefully and I found that in Virtex-6 only the integer division is supported ! I also read an Application note abbout Dynamic Reconfiguration Port for MMCM and PLL but I am confused how to decrease the frequency? Do you have a good reference to help me or can you explain me that, please?
Thank you,

The Virtex 6 PLL will lose lock and will require a reset if you change the clock period you are generating. You can modify all the parameters including the VCO frequency using the DRP but you will lose your clock outputs when you perform the reset. Only phase shifting can be done "on-the-fly" while the design is operating.

If you really need a "on the fly" frequency change then you will likely need to use a VCXO and a DAC to set the frequency that should give you a solution that can set both a precise frequency and depending on the DAC enough resolution to exceed your .5 ns frequency change requirement.

- - - Updated - - -

Hi Dan,

Indeed, I need the frequency change in a small range. The problem stated with Si570 is that for a small change in frequency (Tclknew = Tclkold +Delta t , Delta t = 0.5nsec) the frequency range is 3500ppm which means the frequency can change with the factor of 0.35%. but when I add 0.5nsec to the period of a 600MHz clock signal (i.e. 1.66nsec), the frequency will change with the factor of 30%. It means that Si570 is so far than this value. Is there any alternative for that?

Thanks,

The 3500ppm is the frequency variation during the settling time. If you can't tolerate settling time then you'll need to rethink what you are trying to do.

If you are trying to switch seamlessly (no glitches) between two clock frequencies then you may have to have two VCXOs like that Si570 and set the second to the frequency you are going to switch over to and then wait out the settling time. Xilinx actually has a clock mux that is guaranteed to not glitch when switching between two clocks. It has logic to shut off the clock being switched from during its low time before enabling the clock being switched to getting enabled during its low time. In this way you could easily hop the frequency of the clock around with no glitches, but you'll have to wait for the Si570s to settle each time you change the frequency of the clock you are switching to.

 

[msdarvishi]

The Virtex 6 PLL will lose lock and will require a reset if you change the clock period you are generating. You can modify all the parameters including the VCO frequency using the DRP but you will lose your clock outputs when you perform the reset. Only phase shifting can be done "on-the-fly" while the design is operating.

If you really need a "on the fly" frequency change then you will likely need to use a VCXO and a DAC to set the frequency that should give you a solution that can set both a precise frequency and depending on the DAC enough resolution to exceed your .5 ns frequency change requirement.

- - - Updated - - -


The 3500ppm is the frequency variation during the settling time. If you can't tolerate settling time then you'll need to rethink what you are trying to do.

If you are trying to switch seamlessly (no glitches) between two clock frequencies then you may have to have two VCXOs like that Si570 and set the second to the frequency you are going to switch over to and then wait out the settling time. Xilinx actually has a clock mux that is guaranteed to not glitch when switching between two clocks. It has logic to shut off the clock being switched from during its low time before enabling the clock being switched to getting enabled during its low time. In this way you could easily hop the frequency of the clock around with no glitches, but you'll have to wait for the Si570s to settle each time you change the frequency of the clock you are switching to.

Thank you for your nice explanation and advise. You clearly defined the constraints in this way. Can you please let me know if I use two Si570 chips, how can I toggle between two frequencies? AS I understood, one chip must be set at the frequency of 460 MHz (Tclk = 1.66nsec + 0.5nsec =2.16nsec). and the circuit implemented into FPGA is operating at 600MHz. What is the frequency that the second chip must be set? Is it 600MHz??

Thank you,

 

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Thank you for your nice explanation and advise. You clearly defined the constraints in this way. Can you please let me know if I use two Si570 chips, how can I toggle between two frequencies? AS I understood, one chip must be set at the frequency of 460 MHz (Tclk = 1.66nsec + 0.5nsec =2.16nsec). and the circuit implemented into FPGA is operating at 600MHz. What is the frequency that the second chip must be set? Is it 600MHz??

Thank you,

Setting the two Si570s to 460 MHz and 600 MHz is certainly the simplest way to do this. If the frequencies are never going to change it might be simpler to purchase a fixed frequency device like the Si500. I was thinking you would be moving the frequency around more than just two fixed frequencies.

If they are fixed then just setting them to the correct frequency should be good enough, switching your FPGA clock between the two frequencies is simply a matter of adding the BUFGMUX primitive to your design, which performs that glitchless clock switch. You'll then need a separate control signal to switch between the two clocks in the FPGA. I'm assuming at this point you won't be using a PLL or MMCM as that would defeat the whole purpose of adding those VCXOs.

and the circuit implemented into FPGA is operating at 600MHz.

I'm not entirely sure if you mean that the FPGA starting off with 600 MHz clocking can be switched to 460 MHz clocking (and vice versa), if not then what I've been suggesting probably isn't what you want.