Dynamic Power doesn't scale by frequency

[hansiglaser]

Hi!

I'm doing a post-P&R power analysis using Design Compiler "report_power" after reading in a SAIF file generated with QuestaSim simulating the post-P&R netlist with annotated delays from an SDF file.

If I use a 100x higher frequency in simulation, the dynamic power only increases by approx. 32-37 (depending on use case). I checked the SAIF files which only differ in "DURATION" and for each net "T0" and "T1" (each is 100x lower), but have identical "TC" (i.e., switching count).

This means that it is not possible to "extrapolate" from a slow simulation run[1] to a higher frequency of the final chip.

Could you please help me find why there is not an increase of dynamic power by a factor of 100?

Thanks
Hansi

[1] I simulate an external sensor (ADT7310) which requires 240ms delay between request and response. To reduce simulation time I use 100kHz clock for simulation and a value of 24000 for a delay counter. On the final chip I will use 10MHz and a value of 2400000 for the delay counter.

 

[erikl]

Could you please help me find why there is not an increase of dynamic power by a factor of 100?

Are you sure you get values for dynamic power (only), or are the given values actually for total power consumption, i.e. static+dynamic power?

 

[hoanglongroyal]

hi friend,
if you run your design 100x , I wonder 2 things here:
1. did you check resolution of simulation ? if your period lower than the resolution, so the simulation might not perform correctly
2. your design is close with normal freq, if you pick up it to 100x freq, surely your design will be failed

[1] I simulate an external sensor (ADT7310) which requires 240ms delay between request and response. To reduce simulation time I use 100kHz clock for simulation and a value of 24000 for a delay counter. On the final chip I will use 10MHz and a value of 2400000 for the delay counter.

you increase the freq, and increase the delay also --> if in 1s you saw 100 toggle in normal freq, then you also see 100 toggle in new freq because of ratio delay/freq. this is just my thought.

 

[jbeniston]

Did you update your create_clock definitions? They could be overriding the simulation data.

 

[hansiglaser]

Hi!

Thank you for your valuable replies!

@erikl: Yes, I double checked that I look at the dynamic power only. Here is the report_power output for 100kHz:

Global Operating Voltage = 3.3  
Power-specific unit information :
    Voltage Units = 1V
    Capacitance Units = 1.000000pf
    Time Units = 1ns
    Dynamic Power Units = 1mW    (derived from V,C,T units)
    Leakage Power Units = 1pW


  Cell Internal Power  = 226.3002 uW   (47%)
  Net Switching Power  = 253.0959 uW   (53%)
                         ---------
Total Dynamic Power    = 479.3961 uW  (100%)

Cell Leakage Power     =  93.7467 uW

whereas the output for 10MHz is

  Cell Internal Power  =  11.1608 mW   (62%)
  Net Switching Power  =   6.8402 mW   (38%)
                         ---------
Total Dynamic Power    =  18.0010 mW  (100%)

Cell Leakage Power     =  93.7467 uW

with a factor of 18mW/479uW = 37.6 instead of 100.

Interestingly, the ratio between cell internal and net switching power changes a lot.

@hoanglongroyal:
The simulation resolution is 1ps, IMHO small enough.

In synthesis I use 10MHz as clock frequency, so 100kHz is lower than the target frequency. This means that I don't overclock the circuit at 10MHz, but underclock it at 100kHz.

create_clock -waveform {0.0 50.0} $port_clk -period 100.0 -name "CLK"

For the power analysis, I read in the post-P&R SDC file, which also defines the clock with 10MHz.

@jbeniston: Due to the create_clock with 10MHz and the SAIF file with only 100kHz, Design Compiler complains (when propagating the switching activity, either with propagate_switching_activity or with report_power) with the following warning:

Warning: The derived toggle rate value (0.020000) for the clock net 'Clk_i' conflicts with the annotated value (0.000200). Using the annotated value. (PWR-12)

@all: Thank you for sorting out errors, but I'm still confused why 100x frequency only results in 37x power.

I still have to do measurements (next week), but earlier measurements with simple microcontrollers and with an older testchip with a different process showed a nice linear relationship between frequency and power. Therefore currently I suspect that Design Compiler is doing something smart here, which I don't yet know how to control. Do you have any ideas?

Thanks
Hansi

 

[hansiglaser]

Re: Dynamic Power doesn't scale by frequency [SOLVED]

I still have to do measurements (next week), but earlier measurements with simple microcontrollers and with an older testchip with a different process showed a nice linear relationship between frequency and power. Therefore currently I suspect that Design Compiler is doing something smart here, which I don't yet know how to control. Do you have any ideas?

Great news! Now I get a nice factor of 100.

The only thing I changed was that I added the "-all" switch to the ModelSim "power report" call. This includes all signals in the SAIF file, even if they had no switching activity. Now the SAIF files are much larger (approx. 9-10MB compared to previously approx. 1-2MB).

So, I suspect that Design Compiler, while propagating the switching activity for all nets without switching activity annotation was assuming the fast 10MHz clock, even when doing this for my SAIF files at 100kHz. Therefore the 100kHz values were over-estimated by a factor of approx. 3 which therefore resulted in a factor of only 37 between 10MHz and 100kHz.

Now that the SAIF file specifies information on all nets, switching activity propagation is much faster (only 0.1sec or so, previously it was a few seconds) and there is no degree of freedom for DCs phantasies on switching activity.

Bye
Hansi