[SOLVED] Dynamic latched comparator

[Vlad Cretu]

Hello,

I have a basic question, but it seems that i cannot find it's answer.

Assuming we would have a dynamic latched comparator such as the one presented in https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=210039 Figure 2(a).

How would you quantify the hysteresis of such a circuit (because of the latch) and add hysteresis?


Thank you,
Regards,
Vlad

 

[dick_freebird]

At ATE test, I expect we would ramp (step) the input difference
upward, record first "1" and then from a positive overdrive, ramp
down and record first "0". Then it's arithmetic.

However this is liable to be statistical / noisy numerically and
has never, once, been a clean test development or a totally
clean production test solution as far as my recollection goes.
You might need to work based on larger samples and median
type statistics (mean, I like less than median when there are
gross "fliers" in the distribution).

If you made a fairly slow, self-oscillating RC feedback loop
(slow, meaning that comparator prop delay is inconsequential,
and an A=100 op amp can gain up the input voltage without
adding significant error) then a classical op amp test fixture
loop, could be "sniffed" with the ATE pin for gained-up
VIHD/VILD values, strobed by comparator change-of-state.
Comparator clock would want to be many decades faster
than the oscillation period.