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DWR for PCI memory write cycles?

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it_boy

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PCI Memory write cycles

Hi
can somebody tell me if delayed writes are supported for memory write transactions in PCI. The PCI spec says
"Memory Write and Memory Write and Invalidate commands must be posted (PMW) and not be completed as DWR"
But some of the locally available PCI chips support DWR for memory write cycles. Will it be violating the specification if this option is used in a PCI system
Thanx in advance
 

sam_b31

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Hi,

normally you can delay a write by a maximum of 16 wait state, if the wait state exceed 16 then you must issue a retry completion if you cannot post the write access. When a retry completion you must save the address, byte enable and the data and complete the access when a PCI master access to the same address with the same data (probality to be the same master is near 100%).

:)
 

it_boy

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Hi sam_b31,

Whatever you have posted is the definition of "delayed write". As I have explained above, I want to know if a memory write command can be a delayed write.

Thanks,
it_boy
 

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