Hi,
A school project?
TTL levels are >2V / <0.7V ... but they may go up to 5V / 0V. This is a huge source of error., because you can´t rely on the voltage level.
Therefore I recommend to use a CMOS analog SPDT sitch with TTL logic input levels.
NC to to GND
NO to VCC
COM = output
At the output connect a second order low pass filter (simple RCRC) to attenuate ripple and get almost pure DC signal that is proportional to duty cycle.
Use a cutoff frequency of about 25Hz, this results in a ripple of less than 1mV.
This signal is one input of a comparator.
The other input is an adjustable voltage divider (connected to VCC to GND) and a noise filter capacitor to adjust thresold level.
Feedback the comparator output with an appropriate resistor to get the desired hysteresis.
--> one comparator, no flip flop
If you are in any doubt, then you should give a more detailed description with a picture of the signal flow, timing and so on..
Klaus