I m thinking what kind of circuit that it will be??
correct me if i m wrong!!
i m having few ckts in my mind!!
1)whenever there is +ve edge then it generate a pulse of the above period.. for this kind of ckt duty cycle will be more than 50%
2)Anding the clk with the delayed clock!
for this scenario, duty cycle will be reduced by the delayed version... so, duty cyle will be less than 40% for 200MHz..