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Duty cycle correction.

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vlsi_freak

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Hi..

I have a block whose input frequency is 100 Mhz. Now the same signal is taking out from the block, but its duty cycle is changed to 40 %.

Now, i suppose i am changing my input to 200 Mhz, will there be any chane in the duty cycle. If so how can we calculate the duty cycle variation.

Heard like this is a famous interview questio,,

Awaiting your response.

Thanks
 

tukken

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30%,the duty cyle is 30%
 

pra

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Tukken .. cud u please explain it??

I m thinking what kind of circuit that it will be??
correct me if i m wrong!!
i m having few ckts in my mind!!
1)whenever there is +ve edge then it generate a pulse of the above period.. for this kind of ckt duty cycle will be more than 50%
2)Anding the clk with the delayed clock!
for this scenario, duty cycle will be reduced by the delayed version... so, duty cyle will be less than 40% for 200MHz..
 

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