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[SOLVED] dump reg variables in VCD file

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razi_seyyedi

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Hi friends,

I have a simple testbech with these signals:

reg rst, clk;
wire line1, line2;
wire outp, overflw;

In the do file I wrote (I know I could have simply written that as: vcd add /tb/*):
vcd add /tb/rst
vcd add /tb/clk
vcd add /tb/line1
vcd add /tb/line2
vcd add /tb/outp
vcd add /tb/overflw

then the Modelsim complains that there is no object as 'rst' or 'clk'.

When I change my commands to:
vcd add -r /tb/*
OR
vcd add -r /*

I have all the variables I don't want recursively from inner modules including 'clk' and 'reg' but in the "$scope module dut" which is the module I've instanciated.

Any help would be appreciated.

Cheers,
Emad

- - - Updated - - -

Simple solution
I added those signals from the inner modules:
vcd add /tb/dut/reset
vcd add /tb/dut/clock
 

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