Dummy Pattern on your chip

[sharkies]

I'm in the process of putting dummy patterns on my chip
Chip includes digital baseband... analog baseband and RF blocks
It's a transmitter basically..

anyways.. I excluded dummy patterns on all analog blocks and RF blocks and including high signal frequency path such as the LO signal that comes from off chip and the 2GHz transmitter output signal that will be going off chip.

Are there other issues that I should consider?
The dummy covers ESD, but I didn't put dummies between the pads fearing that it would cause a lot of parasitic capacitance....

The cautions that I took give tons of density rule error in the DRC. I believe that clearing all DRC may be impractical, but how many violations can be tolerated?

Will TSMC put in dummies manually if the believe it needs more?

 

[dgnani]

Hi sharkies

it would be important to specify which process node you are using since local density becomes more and more important as feature size shrinks.
The foundry will add dummies unless you specify otherwise either by verbal/written requirement at submission time or by placing specific exclusion layers in the design

Usually FEOL dummies are most important for yield. We have often ignored metal density rules w/o major impact but we do R&D so price per die is irrelevant.
In most cases you can specify large minimum distance between dummies and design structure to minimize additional parasitic capacitance.
Ideally you should extract and re-simulate.

 

[dick_freebird]

You might consider making your "dummies" be unconnected
(or ground-only) devices and circuit blocks, if this is a part
headed for production on a tight timeline. Spare tire in the
trunk, like. Make yourself small spares blocks that have useful
logic gates and uncommitted transistors, resistors, caps, etc.
Spread them around so you can reach them easily in a metal-
only mask respin.

Dummy-to-dummy-to-dummy leapfrog series capacitance is
likely well less than the bondwires.

I can't remember the last time I was density clean. Some rules
are just ridiculous at some foundries. Especially stuff like wanting
2% via density. If you want a laugh, make a "test chip" consisting
of nothing but density fills and see if that passes, or by how
much. If the density fill cell doesn't pass density, you can forget
it.