In many CMOS processes, the digital part works at 1.8v but there is also 3.3V for analog mainly.
LVDS standard requires 1.2V common mode and 0.4 diff. That is quite complicated to get with 1.8V +-10%. That's why the input of the lvds tx is 1.8V (digital) but later it is shifted up to the 3.3V domain
I've read some papers about this.
You can change the two p-mos of the h-bridge for two current sources to have the same current and Vcm with less vdd.
But it's only necessary for vdd<2.5 V