Aug 16, 2007 #1 G gold_kiss Full Member level 4 Joined Sep 11, 2002 Messages 211 Helped 7 Reputation 14 Reaction score 4 Trophy points 1,298 Activity points 1,789 single port ram dual port ram Hi all, Anyone has designed Dual Port SRAM using 2 single port SRAM? Please give references. Thanks, Gold_kiss
single port ram dual port ram Hi all, Anyone has designed Dual Port SRAM using 2 single port SRAM? Please give references. Thanks, Gold_kiss
Aug 16, 2007 #2 D darylz Full Member level 2 Joined Mar 24, 2005 Messages 129 Helped 5 Reputation 10 Reaction score 1 Trophy points 1,298 Activity points 1,975 single-port dual-port sram difference 1. You can use TWO single port RAMs to generate a dual-port RAM: one for even address and another one for odd address.
single-port dual-port sram difference 1. You can use TWO single port RAMs to generate a dual-port RAM: one for even address and another one for odd address.
Aug 16, 2007 #3 lostin_eda Newbie level 6 Joined Aug 16, 2007 Messages 12 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,366 sram single port divide the address into 2 parts. e.g 4 width address.0000 ~ 1111 0000~0111 can be the first ram's address and 1000~1111 can be the second ram's address. so. the MSB is the enable signal of each ram. when 0 , ram 1 is enabled when 1, ram 2 is enabled
sram single port divide the address into 2 parts. e.g 4 width address.0000 ~ 1111 0000~0111 can be the first ram's address and 1000~1111 can be the second ram's address. so. the MSB is the enable signal of each ram. when 0 , ram 1 is enabled when 1, ram 2 is enabled
Aug 16, 2007 #4 G gold_kiss Full Member level 4 Joined Sep 11, 2002 Messages 211 Helped 7 Reputation 14 Reaction score 4 Trophy points 1,298 Activity points 1,789 Thanks for your replies. But what I need is true Dual Port SRAM. In-a-sense read and write to two different ports can happen simultaneously. Wht explanation you have provided just adds the depth of SRAM kind of address concatination. Thanks, Gold_kiss
Thanks for your replies. But what I need is true Dual Port SRAM. In-a-sense read and write to two different ports can happen simultaneously. Wht explanation you have provided just adds the depth of SRAM kind of address concatination. Thanks, Gold_kiss