dual clock ram in vhdl

[Robin Khosla]

i want to make a ram in which data is written in one frequency CLKA and read fom RAM in some other frequency CLKB...
but i am getting error of multiple driver on we signal in the following code....

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ram is
port (CLKA,CLKB : in std_logic;
DI : in std_logic_vector(15 downto 0);
DO : out std_logic_vector(15 downto 0));
end ram;

architecture ram2 of ram is
type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0);
signal RAM : ram_type;
signal WE : std_logic;
signal AW,AR : std_logic_vector(5 downto 0);
begin
process (CLKA,WE)
begin
if (WE = '0') then
if (CLKA'event and CLKA = '1') then
if (AW="111111") then
AW <="000000";
WE <= '1';
else
RAM(conv_integer(AW)) <= DI;
AW <= AW + "000001";
end if;
end if;
end if;
end process;

process (CLKB,WE)
begin
if (WE = '1') then
if (CLKB'event and CLKB = '1') then
if (AR="111111") then
AR <="000000";
WE <= '0';
else
DO <= RAM(conv_integer(AR));
AR <= AR + "000001";
end if;
end if;
end if;
end process;
end ram2;





if i make another process as shown below for WE in the above code, then code goes on synthesis for days and never ends (i think it goes in infinite loop)

process(clk)
begin
if aw ="111111" then WE <='1'
elsif ar="111111" then WE <= '0';
end if;
end process;

can anyone solve this issue????

 

[TrickyDicky]

You cannot assign WE from both processes. You should have a separate WE for each port of the ram.
Also, WE should be read inside the clock for a synchronous write enable, not an async write enable - afaik no FPGAs have async we's on their rams (so it will not infer a ram properly).

I suggest you read the coding guidelines for your selected FPGA vendor. Its synthesising for a long type because you're not following the guidelines and it is trying to put your ram in registers and not actual rams.

 

[Robin Khosla]

But i need to do this because in my project
i want to write ram at CLKA and when the RAM is full , then i want to read the same RAM at CLKB.

is this possible??

 

[TrickyDicky]

Yes you can. But you cannot control WE from two processes. You'll have to do things "properly" and detect when the ram is full.

 

[Robin Khosla]

ok
but if i will not use we signal in both the processes then how will i detect that the ram is full and when to read



i tried to use fsm by defining a state signal but got same problem

 

[TrickyDicky]

you will need to check the write addresses, and you will need to safely pass it over the clock domain boundary. Or you could just pass the WE signal over the boundary and read that. Theres no need to set it from both clocks (the clkB only reads the ram).