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Driving Serial LVDS LCD's

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Aug 10, 2009
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I am able to buy the iPhone 3GS LCD's at a ridiculously cheap price but have no idea how fast of a clock they need and how to interface with them.

I have seen many LVDS chips out there and some SBC's such as the Beagleboard that is capable of H/Vsync output, 80/86, raw RGB and LVDS on an HDMI port but when I want to hook up my own ARM micro or FPGA I am unsure what things I need to know and what speeds to clock things at. **broken link removed** is a good example. I have seen it in a 7" 800x480 LCD datasheet so I know that its an appropriate chip to use.

For example, on page 18 they have the LCD in 6bit mode with 3 data lanes and it is transmitting 6bits for every LVDS clock cycle. I would have thought that should be one clock cycle per bit on the LVDS side and one cycle on the serializers clock input. So a 6:1PLL. The only way I see this working is if the LCD's deserializer has that 6:1PLL on its die. Ignoring that for a moment page 23/24 shows the LCD timing with porches. total horizontal clocks is 1024 and horizontal is 525 so to display 30FPS I require a 16MHz clock. (1024x525x30) They spec 32MHz for a 60Hz refresh rate but I'm happy to get 30.

So really How do you figure out the input requirements to drive a LVDS LCD? When I have got that down then I can work on finding a chip that you can get in qty <10k!

Hardware breakdown of iPhone 3GS
**broken link removed**
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your LCD can work at 8bit or 6bit mode depending on your selection at FRC and MSL pins. To drive it in 8bit mode you need something like this **broken link removed**.
Thine's chip may be drive it but i am not sure how to input H/Vsync, Data Enable signals on that chip.
By the way LCD that you specified has the vertical refresh at 60hz. I amnot sure if it works properly at 30Hz.
In general all LCDs have similiar LVDS interfaces. 1 clk pair and several data pairs (depend on number of color bits). 7 data signals is output in serial per clk period.
Some needs H/V sync signals embedded in LVDS signals, some ignores them and only Data Enable signal is enough.
Does it help?

Thanks for the reply. I figured the PLL was their to sample the data into the serial stream and a matched bit clock I thought I was reading it wrong that its ~7bits per LVDS clock. I'm going to need to do some accordion traces on those lines to avoid skew with an asynchronous clock.

The H/V sync and DE signals embedded in the serial stream is going to be quite difficult to discover by hand without a decent datasheet. I am considering putting the who prototype on an FPGA and putting a test pattern in memory for it then tweak the bit arrangement and clocks until I get a working system. I will need to buy a well known LVDS LCD panel too for proper testing. Or I could just get a $135 Beagleboard and do it all in Linux software.

Hello, i'm new here.

I'm designing a hobby project with xilinx FPGA and a TFT display from a dead desktop PC monitor.
My goal is to display video from analog Composite source, using Analog's ADV7180 SD video decoder. The TFT display which I would like to use (hsd190men3) has 1280x1024 pixel resolution, 24bit RGB, dual LVDS. The odd and even pixels are sent simultaneously in another LVDS channel.

Because it has bigger resolution that I ever need, I tought it will be ok to send the same data on the even and odd channel, reducing the horizontal resolution.

The LVDS driver what I would like to use is the DS90C385. This chip can handle one of the two LVDS channels. Because of this I need 2 of this IC, feeding the two chip the same signal.

So this leads to my question: Should I use two of this ICs feeding them with the same signal (the disadvantage: more cost, complicated PCB), Or I could just use one IC and connect its outputs into the LCD-s even and odd pixel LVDS channel inputs simultaneously? (I would like to do the last alternative :grin: )

Thank you

Do you want to drive TFT just attaching the LVDS tranmitter to video decoder (ADV7180)? In this case i think you would have some problems on the screen.
Becasue SD analog composite video is interlaced, but you need to drive TFT in progressive mode. To have a complete and meaningfull picture you need an deinterlacer and also a scaler befor the LVDS TX. Because native resolution of SD signal is V576, 720H, since it is interlaced, each field 288 vertical lines before a vsync.
But you screen is much more, so you need to scale it first to fit on screen.
If you don't scale it up -it depends on your TFT- it might appear at left up corner maybe...

After these commends, come to your question, i think TFT might do a copy of your odd pixel data to even pixels if you connect the same data lines to both channels. In this case for example an "I" letter in one pixel width will be seen as two pixels width on screen. And imagine about an "A" letter.
This is just an estimation, i have never seen or try smthg like this.
Good luck.

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