iceblu3710
Member level 3
I am able to buy the iPhone 3GS LCD's at a ridiculously cheap price but have no idea how fast of a clock they need and how to interface with them.
I have seen many LVDS chips out there and some SBC's such as the Beagleboard that is capable of H/Vsync output, 80/86, raw RGB and LVDS on an HDMI port but when I want to hook up my own ARM micro or FPGA I am unsure what things I need to know and what speeds to clock things at. **broken link removed** is a good example. I have seen it in a 7" 800x480 LCD datasheet so I know that its an appropriate chip to use.
For example, on page 18 they have the LCD in 6bit mode with 3 data lanes and it is transmitting 6bits for every LVDS clock cycle. I would have thought that should be one clock cycle per bit on the LVDS side and one cycle on the serializers clock input. So a 6:1PLL. The only way I see this working is if the LCD's deserializer has that 6:1PLL on its die. Ignoring that for a moment page 23/24 shows the LCD timing with porches. total horizontal clocks is 1024 and horizontal is 525 so to display 30FPS I require a 16MHz clock. (1024x525x30) They spec 32MHz for a 60Hz refresh rate but I'm happy to get 30.
So really How do you figure out the input requirements to drive a LVDS LCD? When I have got that down then I can work on finding a chip that you can get in qty <10k!
Hardware breakdown of iPhone 3GS
**broken link removed**
I have seen many LVDS chips out there and some SBC's such as the Beagleboard that is capable of H/Vsync output, 80/86, raw RGB and LVDS on an HDMI port but when I want to hook up my own ARM micro or FPGA I am unsure what things I need to know and what speeds to clock things at. **broken link removed** is a good example. I have seen it in a 7" 800x480 LCD datasheet so I know that its an appropriate chip to use.
For example, on page 18 they have the LCD in 6bit mode with 3 data lanes and it is transmitting 6bits for every LVDS clock cycle. I would have thought that should be one clock cycle per bit on the LVDS side and one cycle on the serializers clock input. So a 6:1PLL. The only way I see this working is if the LCD's deserializer has that 6:1PLL on its die. Ignoring that for a moment page 23/24 shows the LCD timing with porches. total horizontal clocks is 1024 and horizontal is 525 so to display 30FPS I require a 16MHz clock. (1024x525x30) They spec 32MHz for a 60Hz refresh rate but I'm happy to get 30.
So really How do you figure out the input requirements to drive a LVDS LCD? When I have got that down then I can work on finding a chip that you can get in qty <10k!
Hardware breakdown of iPhone 3GS
**broken link removed**
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