Aug 8, 2008 #1 R Renjith Full Member level 3 Joined Jan 3, 2005 Messages 173 Helped 15 Reputation 30 Reaction score 6 Trophy points 1,298 Location India Activity points 1,710 Hi, How to write the verilog testbench to drive a value to a bidirectional port. Can someone suggest a simple example. assuming a module has a bidirectional bus, clk,enable, RW Thanks in advance Renjith
Hi, How to write the verilog testbench to drive a value to a bidirectional port. Can someone suggest a simple example. assuming a module has a bidirectional bus, clk,enable, RW Thanks in advance Renjith
Aug 8, 2008 #2 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,566 Helped 14,761 Reputation 29,805 Reaction score 14,139 Trophy points 1,393 Location Bochum, Germany Activity points 298,733 I'm not using Verilog for testbenches, so I can't give an example. (I assume, Verilog textbooks do). But it's rather simple, you can drive either 0,1 or Z to each bit of the bus, as in a hardware test.
I'm not using Verilog for testbenches, so I can't give an example. (I assume, Verilog textbooks do). But it's rather simple, you can drive either 0,1 or Z to each bit of the bus, as in a hardware test.
Aug 8, 2008 #3 P pwq1999 Member level 2 Joined Mar 2, 2008 Messages 42 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,578 you can use the "trireg",and maybe the link below can help you!