Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] drc violation issue relation with tapeout of chip

Status
Not open for further replies.

cyrax747

Full Member level 3
Joined
Nov 8, 2012
Messages
167
Helped
13
Reputation
26
Reaction score
11
Trophy points
1,298
Location
Bangalore
Activity points
2,494
Timing is clean, but you've 1 DRC violation.Can we tape-out the design?
 

There's a reason DRC is called Design Rules Check is because if you violated the design rules you run the risk of having a design that: works by luck, works intermittently, or fails to work. Take your pick.

Isn't this something that should be brought up with the ASIC lead on the project instead of as a post on edaboard? Or is the designated ASIC lead on the project not really an experienced senior level ASIC engineer (i.e. decades of experience)?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top