Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

drc violation: contacts must be covered in Met1

Not open for further replies.


Advanced Member level 4
Jun 12, 2003
Reaction score
Trophy points
Activity points
drc violation

It's my 1st time at layout and when it's completed, I got this error message by running DRC:

"Error All Contacts must be covered in Metal 1"

Looking at the layout, the errors occurred at all places where there's a contact layer on
1. poly & met3 layers
2. nselect & met5 layers

Anyone can enlighten me?

cannot match terminal counts

Put the rectangles of metl1 covering the contacts, wherever the error is. The error will go.

drc violation definition

Make sure tht contacts are covered with respective layers.
For example Via 1must be covered with both Metal 1(down layer) and Metal 2 (upper layer).


metal 1 drc violations

Each contact must be covered with its respective metal or metals for the connection to be valid. And this metal must overlap the contact or via.
Certain times when u are connecting a lower level metal to higher level metal all the intermediate metals and vias must be added. Even if one layer is missing DRC is violated.
Ex: Connect metal 2 to metal 5.
note: all metals must overlap their respective vias. minimum overlap is determined by the foundry.

Get back if the error does not clear.

drc violations

cont should always be covered by Metal1.
as the connection b/w poly and metal1 or diff and metal1 is always through cont.

similarly via1 b/w M1 n M2 and so on ....

missing drc

All comments are appreciated & I've fixed most of the problems by now. I have clean DRC but when it comes to extraction, this error occurs:

"Cannot match terminal counts for nhp ivpcell TSMC018"

What does it mean? The error occurs at all poly layer which formed transistor.

terminal counts

this is siva
The contact should cover through the metal1 by some distance in all sides where u got this error.

ok u have any doubts ask me through this website


Added after 14 minutes:

this is siva
DRC Rules are given by the fab so we can clear the drc violations but lvs violations are generated differently for designer to designer .According to my knowledge u have mismatching of terminals (nodes) between schmatic and layout.So plese verify ur logwindow and verify ur schmatic nodes and layout nodes.If u got any net mismatch then connect that particular net to required net that is according to schmatic design.

Nope, i'm talking about extraction and not LVS here. Extraction fails with the error mentioned and no file generated.

respective via must be naot only covered with the metals but also there should be some minimum extension in all sides.

For example Via12 must be completely covered with Metal 1 and metal 2 and there should be minimum extension of the M1 and M2 specified by the DRC rules.(generally its around 0.01 um)


check the definition of the mos extraction.
You may need to specify some special layer to extract special mos.

Its depends on the design rules that created by your foundries....

There must be metals ENCLOSED your via else the connection "via" wont be valid...

Metal1 must enclose contact, metal2 for via1, metal3 for via2...
Open your DRM at 'Contact'.

Not open for further replies.

Part and Inventory Search

Welcome to