DRC - LVS on nangate library

[simopoulos]

(Reposting this thread as I did not have any replay -- need help on this)

I have downloaded the nangate library and I want to test a layout (that I have synthesized on this library via synopsys and imported it to virtuoso).

How can I run DRC and LVS checks? I cannot find any rule files.

Thanks

 

[saurabhr8here]

I believe the Nangate library provides .LIB files with timing information for 45nm node (correct me if I am wrong). You will not get a DRC/LVS decks with the library.

 

[simopoulos]

Thanks for the reply.
However if I wanted to make a core (IP), what I would do is to synthesize using the .db files, import the result to encounter, import the result of the encounter to virtuoso and characterize the design that is imported to virtuoso. How can I be sure that the core is DRC/LVS free?
Does the library guaranty that the result will be DRC/LVS free? Do I need an extra tool to verify?
Thanks.

 

[saurabhr8here]

Well, the .lib file will only give you an estimate of timing/power/leakage after synthesis. It will give you an estimate of area, but to get a complete picture you do need layouts of the standard cells and need to go through complete place and route. I believe that the Nangate 45nm was created using ASU PTM 45nm model files and NCSU OpenPDK layout, you can probably search online or inquire from Nangate regarding their layouts. I do not know if a DRC/LVS deck was supplied with it or if the library was created from layouts that were DRC error free. Since most of the data is open-source I am not sure what kind of DRC you'd use because in most cases, these are provided by foundries.

 

[gbmoura]

hi,

You can use the CAD tool calling Calibre (Mentor) integrated with Virtuoso (Cadence).
Using the design kit NCSU-FreePDK45-1.4.
The design kit have all design rules for DRC/LVS/Extraction with Calibre.

regards,