i think he is asking about the DRC and LVS errors which we usually get after designing the layout...like
open circuit violation, short circuit violation , antenna violation , density check violations and min contact rule and so on am i right?
Hi vlsi,
The poly end cap is an effect that has to do with the POLY etching process, when the photolitography is being done causes some rounding effect on poly lines so, in small MOS (due to selfalign process) it might be an issue...
Solutions: THere are 2
1- In layout realm... TO make bigger MOS transistors in order to minimize the etching effects.
2 - Outside our spectre... There are some processing techniques to minimize the effect.