DRC LVS errors in the ASIC design

[rake.405]

can anyone give some drc&lvs errors in the asic design

 

[layoutmaster]

drc lvs errors

Please elaborate a little more your question. It's not clear what are you really looking for...

 

[vlsitechnology]

drc lvs errors

i think he is asking about the DRC and LVS errors which we usually get after designing the layout...like
open circuit violation, short circuit violation , antenna violation , density check violations and min contact rule and so on am i right?

 

[kumar_eee]

Re: drc lvs errors

Hi vlsitechnology, Yes you are right...

Find some more from my experiance.

LVS:
Open circuit
short circuit
Different no.of Ports
Connectivity Error
Property Error
...... etc

DRC:
Latch-Up violation
Min space Error
Metal Enclosure violation
Fat metal Spacing violation
Poly Endcap violation
..etc..

 

[vlsitechnology]

drc lvs errors

HI kumar wts this poly end cap violation??
how to minimise this?

 

[layoutmaster]

drc lvs errors

Hi vlsi,
The poly end cap is an effect that has to do with the POLY etching process, when the photolitography is being done causes some rounding effect on poly lines so, in small MOS (due to selfalign process) it might be an issue...

Solutions: THere are 2
1- In layout realm... TO make bigger MOS transistors in order to minimize the etching effects.
2 - Outside our spectre... There are some processing techniques to minimize the effect.

 

[moriar]

drc lvs errors

OPC the end.