eladla
Member level 4
Hi,
I am trying to layout a DRAM sense amplifier.
I already have a layout, but I`m sure it`s not optimal,
since I made it without a refrence. It barely fits within the cell pitch.
Can someone please point me to a refrence design or some other such resource?
Thank you!
Edit: I`ll elaborate on my problem. I attached the layout I have so far.
The two pmos transistors are cross-coupled (source to gate) and the sources are connected to bitliens. Now I need to connect both drains together and to an input signal, but without connecting to the bitlines.
How can I do this? Any ideas?
I am trying to layout a DRAM sense amplifier.
I already have a layout, but I`m sure it`s not optimal,
since I made it without a refrence. It barely fits within the cell pitch.
Can someone please point me to a refrence design or some other such resource?
Thank you!
Edit: I`ll elaborate on my problem. I attached the layout I have so far.
The two pmos transistors are cross-coupled (source to gate) and the sources are connected to bitliens. Now I need to connect both drains together and to an input signal, but without connecting to the bitlines.
How can I do this? Any ideas?
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