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DPDT switch CMOS implementation

promach

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May I know how the following DPDT switch CMOS circuit implementation works ?

SPDT_DPDT_switches.png
 

BradtheRad

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Just a guess... It all starts with a SPST? And then you progress in steps until you have DPDT?

So once you put together a mosfet circuit to do SPST, duplicate it to perform symmetrical action (SPDT), and duplicate again so you have DPDT?

It's not readily obvious where the SPST section begins and ends, and what the control signals do. I think the control signal both biases the transistor, and adds DC component to the incoming signal (which is AC coming from the left-hand).

As for the DPDT schematic, there's two overlapped wires in the center, creating a kind of cross-biasing. I suppose the purpose is to turn on the left side which turning off the right (and vice-versa). Perhaps the purpose is also to add a DC component in the signal path.
 

promach

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V(control 3) logic high connects P1 to P3, whilst disconnecting P2 from P4
V(control 3) logic low connects P2 to P4, whilst disconnecting P1 from P3

V(control 4) logic high connects P2 to P3, whilst disconnecting P1 from P4.
V(control 4) logic low connects P1 to P4, whilst disconnecting P2 from P3.

Device M1 and M2 act as grounding devices again to prevent floating voltages.

I tried to replicate the phase shifter circuit which consists of DPDT switch, SPDT switch and some filtering circuit as described in Figure 2 of this paper : A Full X-Band Phased-Array Transmit/Receive Module Chip in 65-nm CMOS Technology using open-source SKY130 PDK.

VsfBrTs.png


It seems to be working (See Vsw3 and Vsw4 ) , with the exception of the first 4 waveforms (red, blue, orange, green)
Could anyone advise ?

WxhleVa.png
 

BradtheRad

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Not that I understand the linked paper...

1.
What is the shape of phase plot do you wish to achieve?

2.
Do you believe the problem is a switching fault?
Or, that L & C values are incorrect?

3.
Can you make a simple circuit that serves to illustrate the behavior you wish to achieve ? And after you make it work properly, use it as a model to pattern the entire project after?

4.
Amount of phase shift is determined by resistance combined with L or C or LC values. It's hard to be sure which resistance plays the chief role in this, whether input resistance or output resistance. Does your simulation have one or the other or both? Are you using a standard value such as 50 ohms at each location? Should it be installed at both input and output?
 

FvM

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I don't understand the simulation setup. What's connected to the ports P1 .. P4 in the #3 circuit. The DPDT switch is for X-band signals, I'd expect respective RF signal sources and loads, in case of doubt with 50 ohm matching.

X-band is 8 to 12 GHz. What's the idea of applying 1 MHz to 1 THz signal in the #4 phase plot?

I't seems like you are not understanding the concept of a switched phase shifter. The specified phase numbers are increments, total phase is irrelevant.

Having said this, I don't know if your simulation circuit is working according to specification. But very surely, your simulation setup is unable to check for.
 

promach

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Why total phase is irrelevant ?

Note: I have already had 50 ohm matching, look carefully.
 

promach

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FvM

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I have no problem with high ohmic resistors required for simulator operation. My point is that the circuit in post #3 has apparently no useful RF signal source nor a termination.
 

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