Downsampling on multi word bus.Verilog experts, please help!

[szakharo]

Downsampling on multi word bus. Verilog experts, please help!

Hello guys,
I am trying to design a downsampler in Verilog which would take 5 samples and output average value at fCLK/5.
Each sample is 8 bit long, however input bus is 4 words long (32 bits). So every clock cycle I am getting 4 new values!
It would be an easy task to create a pipeline if I would be getting only 1 value per clock. But this really drives me crazy, especially considering that I have 4 bytes per clock and they need to be down sampled by 5, so some samples need to come from the next clock cycle.
Any help is greatly appreciated!

 

[TrickyDicky]

This isnt really a verilog question, its an algorithm design question.
Basically you're getting 4 words/clock, and you need 5 words to get a single output. So therefore your output will be 4/5 of the input rate ie. for every 5 input words, you'll get 4 valid outputs. So you just need to create a "valid" signal on the output in parralell with the data to show the next part of the pipeline whats a real output and whats not. GIven your input data, your valid signal will look like:

clk   __--__--__--__--__--__--__--__--__--__--__--__--__

valid ______----------------____----------------____----

data  XXXXX><D0><D1><D2><D3><XX><D4><D5><D6><D7><XX><D8>

 

[szakharo]

Sorry about confusion, you might not understood the question correctly, not sure how would data valid signal help.
Here is what my data stream looks like:

clkIn ______--------_____--------_____--------_____--------______--------______--------_____-------
dataIn XXX><A1A2A3A4><A5B1B2B3><B4B5C1C2><C3C4C5D1><D2D3D4D5><A1A2A3A4><A5XX
clkOut _____--------------------------------------____________________________----------------------
dataOut XX><aver(A1 to A5) aver(B1 to B5) aver(C1 to C5) aver (D1 to D5) ><aver(A1 to A5)

Data in and data out are 32-bit wide, transmitting 4 8-bit words every clock cycle.

 

[TrickyDicky]

ok, I misunderstood. But the algorithm could be done failry easily. Just store the data and sum it - and put some control logic in there to share resources. What do you really want from us? the question is too broad.

 

[szakharo]

ok, I misunderstood. But the algorithm could be done failry easily. Just store the data and sum it - and put some control logic in there to share resources. What do you really want from us? the question is too broad.

Fairly easy? Can you describe the algorithm with a little more details? Forgive me, but I don't have much experience with Verilog/VHDL as I used to program in C where everything is sequential. I don't want to reinvent the wheel or make thing way overcomplicated. If it would be a single byte every clock, then I could read a new value, store it, add to the sum, output sum every 5 clocks and reset sum to zero.
But I have 4 bytes, so every cycle it needs to be something like this:
1. read 1st 4 bytes; add bytes 1-4 and store in sum1
2. read next 4; add byte 1 to sum1; add bytes 2-4 to sum2
3. read next 4; add bytes 1-2 to sum2; add bytes 3-4 to sum3
4. read next 4; add bytes 1-3 to sum3; add byte 4 to sum4
5. read next 4; add bytes 1-4 to sum4; output sum1,sum2,sum3,sum4,sum4

I've tried to come up with an algorithm and control logic, but no matter what I do, seems like I am always at least a cycle behind and my buffer keeps overflowing.

 

[TrickyDicky]

you need to build a state machine that just tracks what position you're at. That way you know which of the 4 inputs go into what addition. This should be easily pipelined so the output can appear a few clock cycles later. Im thinking you could just have first stage of the averager take in between 1 and 4 inputs, and the 2nd stage take the remainder. It will take just 4 2 to 1 muxes, chosing between inputs and 0, with the 2nd stage in pipleine doing the same, based on the state machine state (and the state machine could just be a counter to track the data position offset.) You always know where the data will be, its not random.