Downloading problem in ACTEL FPGA

[vinod_g]

Hi,
I am seeing a peculiar problem, when I dumping the code into ACTEL FPGA. Some times the code is not working properly. But when I recompile and dump into FPGA without any modifications in code, it may work. Why this problem occurs? If occurs what measures we have to take into account. My design is taking around 93% of FPGA.

 

[muni123]

Limit the design occupancy to 75% of the device so that you can find a solution to your problem.
Else choose another Device.

 

[mmarco76]

It seems a clear Timing problems on some part.
Be sure to have given all the constraint you need.

From what you tell it seems that sometimes for how the design is fit your timing are ok and so it works, else other time they fail.

The muni advice still be nice, because with 93% of the device you've to be sure that you'll not have to change too much of the design in a future (but as you know future is always a question mark..)