Down sampling problem

[sureshaa]

Hi all,

My input frequency of a downsampler will be 110 Mhz and I need to down sample to 40 Mhz. I dont have decimal downsampler in altera. So I have planned to upsample my frequency to by 4 (i.e 440) then down sample by 11(i.e 40). But the problem is in altera(stratix V) it is showing 400 Mhz is maximum sample rate i can give to interpolator. Is there any way to down sample 110 to 40? Is any other altera devices will support more than 400?

Thanks in advance,

Suresh.A

 

[std_match]

I suggest that you use polyphase filtering. It is simple if the 40 MHz output rate can be generated from the 110 MHz input rate.
If the 110Mhz and 40 MHz are in different clock domains that are not locked to each other, it is more complicated.

 

[sureshaa]

Hi std_match,

Clock domain is same only.. it is 200 MHz. but me too having the idea of poly phase filtering. but my coll'es are suggesting me, polyphase filter is not recommendable solution. Is there any other way?

 

[zorro]

Hi sureshaa,

let me ask: your clock is 200 MHz and the samping frequency of your input signal is 110 MHz?
So, there is no synchronism between the sampling frequency and the clock?
You have to process some limited blocks of data (i mean not continuously in real time)?
Regards

Z

 

[sureshaa]

Hi sureshaa,

let me ask: your clock is 200 MHz and the samping frequency of your input signal is 110 MHz?
So, there is no synchronism between the sampling frequency and the clock?
You have to process some limited blocks of data (i mean not continuously in real time)?
Regards

Z

Let me clear: My clock frequency is 200 MHz. Input data rate 110 Msps. and Output data rate 40 Msps.

 

[std_match]

Clock domain is same only.. it is 200 MHz. but me too having the idea of poly phase filtering. but my coll'es are suggesting me, polyphase filter is not recommendable solution. Is there any other way?

When the ratio between output and input sample rates is a simple rational number, and the output sample clock can be locked to the input sample clock,
a polyphase filter should be the best solution.
In this case the ratio is 4/11 and you only need 11 "coefficient banks" in the polyphase filter. The filter will only process data at the 40 MHz output rate.

 

[zorro]

Let me clear: My clock frequency is 200 MHz. Input data rate 110 Msps. and Output data rate 40 Msps.

OK; but what about the other 2 questions?

So, there is no synchronism between the sampling frequency and the clock?
You have to process some limited blocks of data (i mean not continuously in real time)?

There can be an issue if the system has to work continuousy and the sampling rates (input and output) are asynchronous.
For the implementation:

When the ratio between output and input sample rates is a simple rational number, and the output sample clock can be locked to the input sample clock,
a polyphase filter should be the best solution.
In this case the ratio is 4/11 and you only need 11 "coefficient banks" in the polyphase filter. The filter will only process data at the 40 MHz output rate.

I agree with std_match, although some solution using CIC fliters could be considered.
Regards

Z