Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Doubts abt DFT Audit & Bed Of nails tester

Status
Not open for further replies.

san2004

Member level 1
Joined
Jun 26, 2007
Messages
40
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,286
Activity points
1,597
Hi,
Currently I am working on one multilayer board (4 layers) in which I have to give provision for Bed Of nails tester. I understood that I have to add via for each net & that will be used for in-circuit testing.
But still I am not clear.. so my question is what precaution I have to take as PCB Designer for bed of nails tester ( settings, routing etc.) & I want to know the basics of DFT audit .I just know that dft means design for test .
Thanks in advance.
 

hyoree

Member level 1
Joined
Jul 11, 2007
Messages
32
Helped
5
Reputation
10
Reaction score
0
Trophy points
1,286
Activity points
1,437
fyi!
pls review and put questions to this title if you have any puzzle.
 

    san2004

    points: 2
    Helpful Answer Positive Rating

san2004

Member level 1
Joined
Jun 26, 2007
Messages
40
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,286
Activity points
1,597
Hi thanks Raj & hyoree for ur replies...
Hyoree I am studying the document u have given & will definately post queries regarding it..
Once again Thanks a lot !!!!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top