Doubts abt DFT Audit & Bed Of nails tester

[san2004]

Hi,
Currently I am working on one multilayer board (4 layers) in which I have to give provision for Bed Of nails tester. I understood that I have to add via for each net & that will be used for in-circuit testing.
But still I am not clear.. so my question is what precaution I have to take as PCB Designer for bed of nails tester ( settings, routing etc.) & I want to know the basics of DFT audit .I just know that dft means design for test .
Thanks in advance.

 

[raj_pcbtech]

This document may answer your question.

Raj

 

[hyoree]

fyi!
pls review and put questions to this title if you have any puzzle.

 

[san2004]

Hi thanks Raj & hyoree for ur replies...
Hyoree I am studying the document u have given & will definately post queries regarding it..
Once again Thanks a lot !!!!