i just designed a cic filter to down sample input signals from 65 mhz to 10 khz. which will give a decimation factor of 6500.
i decided to implement this in cascaded manner :: that is 3 cic filter cascaded together which will have R:20,25 and 13 ?
where the max working register length is 38 bit width, if i selected 5 stages
now question is how can i select the NUMBER OF STAGES in the cic filter..?????
i read few articles and i didnt find any criteria for deciding N.. most of the papers they simply decided the N as 4,5 10 etc
and please excuse me if this is a stupid question
Sounds like you missed a basic introduction to CIC decimators. The number of stages N is the filter order, you can visualize it's effect by looking at the CIC response either in time or frequency domain. In frequency domain, the magnitude characteristic is approximately (sin(x)/x)^N with the first zero at the output sampling frequency, the exact expression is
The filter order is usually commanded by the required suppression of out-of-band signals that are folded into the base band. N=2..4 is reasonable for many applications.
The smooth (sin(x)/x)^N characteristic of CIC decimation filters is often unwanted in signal processing applications, e.g. for oversampling ADC. Therefore a FIR decimator with steep frequency characteristic or a CIC with compensating filter is often preferred for the last decimation stage.
I am using a fir filter in the final stage as compensation filter.
i am doing it iin verilog. so everything i am able to calculate except "N".
my decimation rate is 5600=65Mhz/10KHZ :: and internal width of register is Bin+N*log(RM),, where M=1;
but i got a confusion about how i will decide value of N.
As said, it depends on the required of band suppression by the filter. Need to know the input signal spectrum, characteristic of analog anti-aliasing filters in front of the ADC and acceptable aliased signals.