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doubt regarding pipeline sar adc design

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diaz080

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i was trying to design 3 stage(12 bit)pipeline sar adc(study purpose) in cadence .cleared single stage design.(single ended 4 bit) now i'm stuck.at the end of 4th cycle of sar logic i'm having the error voltage(DAC output) This is the residue voltage which i need to pass to the next stage right ? what are the design criteria of residue amplifier which i need to use here ?

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