Doubt regarding multicycle path setup and hold anlysis

[vikas_33]

Hi,
In our design we r generating 1MHZ clock from 8mhz clock.
There are some logic in design where we are sending data from 8Mhz to 1 MHZ.
Do we need to set multicyle paths for setup and hold check?
Thanks

 

[anssprasad]

I think they should be defined as false paths, since they are clearly crossing clock domains.

 

[ljxpjpjljx]

this two clock are from the same source?

 

[anssprasad]

Hi,

If the clocks are from the same source(when you say you are generating the 1MHz clock from 8 MHz then these two clocks should belong to the same domain) you need to set the 1MHz clock as a derived clock and define the corresponding parameters. When you do this the tool will automatically check the timing of the signals that cross the freq domains.

Thanks
Prasad

 

[michealwolf]

It's no need to set multi cycles etc.
Once you declared generate clock with the correct clock phase. STA will automatically decide the launch clock edge and capture clock edge.

 

[keertiprasad1]

I Believe if there is a generated that is derived from the source clock then its sure that the clocks cannot be asynchronous. And u need to setup a multicycle path because the data may not be captured in 1 clock cycle because ur generated clock is 8 time slower than the original clock. So i suggest take help of designers and try to confirm what MCP to give..


Thanks
Keertiprasad

 

[yx.yang]

Hi, ALL:
Yes, you can set something to let the tool treate these (8MHZ --> 1MHZ and 1MHZ --> 8MHZ) paths as SYNC path, and analysis timing between the path. I can be done.
But the problem maybe: it's hard for tool to fix the hold timing violation (may increase a lot in gate count to fix hold violation).
A better method maybe: design grant these paths are ASYNC path, and add synchronization logic between them.