doubt in VHDL.....?uregent..

[walkman]

subtype UREAL is REAL;
type UREAL_VECTOR is array (natural range <>) of UREAL;
type UREAL_TABLE is array (natural range <> , natural range <>) of REAL;
function resolved (S : UREAL_VECTOR) return UREAL;
subtype RREAL is resolved UREAL;



could you plz any one explain the above lines..i understood first line .but in second line what is meaning of "natural range<>".and i didn't understood 4,5 lines

 

[TrickyDicky]

Someone like silly code.

the first line is one of the most redundant bits of code I have ever seen. why do you make a subtype of real without setting a range you might as well just leave it at real.

the natural range bit is telling users that the range of this vector, when declared, must be anything from 0 to integer'high. So

signal a: ureal_vector(0 to 10); --valid
signal b: ureal_vector(99 downto 66); --valid
signal c: ureal_vector(-1 to 1); --invalid as -1 is not in the natural range.

But then finally someone is resolving the real type. Is this for some model, maybe of an analogue circuit? this code is not synthesisable.

 

[walkman]

Thanks for your reply.. yes it is code for analog modeling not for design just for simulations