doubt in module port map.

[Sasi Cm]

Doubt in port mapping:
How to port map the following module in Verilog. The encoder has the input as x[120:0] and output as y[55:0]. Now the decoder obtain the input from encoder by port mapping. The decoder has the input as a[55:0] and output as b[125:0].
Now how to port map the y and b.

 

[imbichie]

You can connect the encoder's output y[55:0] to the decoder's input a[55:0], simply using a wire.
Here both have same number of bits. So declare a wire of size [55:0] and connect.
You cannot port map y with b. Because both are output.

 

[Sasi Cm]

but i wrote these encoder and decoder as different programs...