Doublt on reading multiple libraries during synthesis ?

[raghavathej]

If i read 2 libraries for synthesis from either slow/fast/typical library, will my design read few gates from one library and few gates form other library at the same time ?

Also, What are the all possible low power options i can give in by Synthesis TCL script?

 

[YuLongHuang]

the libraries you mention are different at operating condition, or called different corners.
For example, slow is 125C and fast is -40C. But they share the same module name.

During the synthesis, you can read lots of library including libraries under the different corners.
However, you have to use "set_operating_condition" to specify the corner.
In this case, the tool will apply the library you specify and ignore the remaining corner to optimize the design.

There are several ways for low power design. Two of the easier are:
1. Clock gating.
try turn on the option -gate during the command "compile"

2. Multiple threshold voltage ( hvt/lvt ) design
make sure that you have the corresponding library first.

Best Regards,
PoLo