double flip flop synchronizer design for clock domain crossing

[kichhu]

Hi
When we use a double flip-flop for dealing with metastability in CDC, although the second one helps to come out of metastability state, it doesnt necessarily give the correct output value right? for e.g., say the first flip flop went into a metastability state while trying to latch a "1" ... a "0" can be seen at the output of the second flip flop after the metastability state is resolved right? If this is correct then how is this handled? to make sure a wrong value is not propogated?

Thanks

 

[FvM]

Metastability happens, if the input is changing while you sample it. In so far, it's impossible to decide if '0' or '1' is the correct value. Thus no "wrong" value will be propagated. Please notice however, that double FF synchronizers work only for single bits, not for aggregates of multiple bits. They demand for other synchronizing means to pass consistent values between domains.

 

[kichhu]

Metastability happens, if the input is changing while you sample it. In so far, it's impossible to decide if '0' or '1' is the correct value. Thus no "wrong" value will be propagated. Please notice however, that double FF synchronizers work only for single bits, not for aggregates of multiple bits. They demand for other synchronizing means to pass consistent values between domains.

Thank you so much for the reply.
Im just wondering over ... so for e.g.: say the transmitter sent a zero and then a one...the receiver is supposed to read zero but due to setup time violation if the data is not read properly and the metastable got resolved into a one.....how will the receiver ever know that the data it read is wrong? or is the main resp of the synchronizer just to make sure no metastability and reading wrong data issue to be taken care by something else?

Thanks

 

[shanmugaveld]

we need to make sure that data 0 is atleast stable for two clocks in the receiver domain before sending 1.
If the receiver fails to receive correct data, we need to use different type of synchronizer to get the correct value.

 

[std_match]

Thank you so much for the reply.
Im just wondering over ... so for e.g.: say the transmitter sent a zero and then a one...the receiver is supposed to read zero but due to setup time violation if the data is not read properly and the metastable got resolved into a one.....how will the receiver ever know that the data it read is wrong? or is the main resp of the synchronizer just to make sure no metastability and reading wrong data issue to be taken care by something else?

Thanks

Since the signal is considered to be asynchronous for the receiving clock domain, it is always possible that it is sampled just before or just after it changes. Both are "correct", so the receiving logic must not depend on the exact position of the incoming edges. There will be some jitter, even without metastability. The metastability synchronizer does not change this, but it guarantees that we get '0' or '1', and not some inbetween value that can cause problems. This means that it doesn't matter if the metastability resolves to '0' or '1'. The result is the same as the normal jitter.

 

[kichhu]

Thanks a lot for all the replies/clarifications.
It will be of lot of help if someone can post any reference or something that has more information on these transmit/receive protocols type stuff used at the multi-clock domain digital design level....esp for I/O circuits

Thanks

 

[nanor000]

Thanks a lot for all the replies/clarifications.
It will be of lot of help if someone can post any reference or something that has more information on these transmit/receive protocols type stuff used at the multi-clock domain digital design level....esp for I/O circuits

Thanks

Look here : Ran Ginosar's Home Page

There is a great tutorial : https://webee.technion.ac.il/~ran/papers/Metastability and Synchronizers.posted.pdf