wait until ((clk'event and clk ='1') or (clk'event and clk ='0'));
won't synthesize to a double edge (raise and fall) flip flop? I get this error
Code:
Error (10628): VHDL error at test3.vhd(9): can't implement register for two clock edges combined with a binary operator
Error (10658): VHDL Operator error at test3.vhd(9): failed to evaluate call to operator ""or""
Also, when I wrote
Code:
wait on clk;
in active-hdl the functional simulation shows a double edge flip flop as below
but quartus shows the following error
Code:
Error (10533): VHDL Wait Statement error at test3.vhd(10): Wait Statement must contain condition clause with UNTIL keyword
I know that is related to synthesis templates that tools use. I would like to know which one is closer to standard.
Because you can only synthesize circuit descriptions that are supported by the target hardware. No modern FPGA supports double clock edges.
You can find emulation circuits for double edge clocking in literature comprised of two single edge FFs and additional combinational logic, but they have bad performance and problems in timing closure.
You may call it a device specific problem. But a very general problem if you don't find any logic device that has double edge sensitive FFs. As you found out, it's possible in simulator, hence no VHDL syntax or semantic problem.
However, legal VHDL isn't necessarily synthesizable.
And often double edge triggered is not useful at all.
What´s your exact application that needs double edge triggering?
...and then: how is timing specified?
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One of a few double edge applications I know is the DDR interface. But for this the FPGAs often have dedicated hardware periferals.
In current FPGAs the benefit of using two clock edges on a single register goes away if you can just double the clock rate on the registers. You get comparable performance and timing requirements.